1. Field of the Invention
The present invention relates to a single chip type microcomputer which can satisfactorily be operated by a battery, and more particularly to an improvement for the purpose of realizing transition to a low power consumption mode without excessive consumption of electric power.
2. Description of the Background Art
In recent years, improvement in the performance and size reduction of home electronic products and information devices have rapidly been performed. Among the home electrical products and information devices, small size portable devices have significantly been improved. One of important elements which have realized the foregoing improvement of the small size portable devices is a single chip type microcomputer. The single chip type microcomputer has a structure that all of circuit elements are packed in one semiconductor chip (a semiconductor substrate). Since the microcomputer has been employed to constitute the small size portable device, integration of elements, size reduction and saving of electric power have been realized. In particular, thanks to the size and weight reduction of a battery which is a power source for the small size portable device, the portability of the small size portable device has significantly been enhanced.
3. Structure of Conventional Device
FIG. 8 is a block diagram showing the internal structure of a conventional single chip type microcomputer as a background of the present invention. A microcomputer 150 has main portion of the circuit elements, that is, a main circuit which includes a CPU (Central Processing Unit) 5, an ICU (Interruption Control Unit) 6, a memory 7, an input/output interface 8 and a peripheral circuit 9. The CPU 5 performs calculations in accordance with a program. The memory 7 is a semiconductor storage device in which a program which is executed by the CPU 5 and data which is read and/or written by the CPU 5 are stored. The memory 7 represents all of ROMs and RAMs which can be accessed by the CPU 5.
The input/output interface 8 controls input and output ports for supplying/receiving data to and from an external unit, i.e., functions as an interface for the external unit. The input/output interface 8 includes a parallel interface and/or a serial interface. The peripheral circuit 9 usually includes a timer, an analog-to-digital converter, a digital-to-analog converter and a pulse width modulator.
The ICU 6 controls an interrupting process of the CPU 5. The ICU 6 receives an internal request signal IR transmitted from a timer or the like of the peripheral circuit 9 and supplied through a signal line 91 and receives an external request signal ER supplied through an external terminal 13. The ICU 6 transmits, to the CPU 5, a control signal through a signal line 65 in response to the internal request signal IR and the external request signal ER.
Both internal request signal IR and external request signal ER are signals for requesting the CPU 5 to perform the interrupting process, that is, interruption request signals. The internal request signal IR is generated in the microcomputer 150, while the external request signal ER is supplied from outside of the microcomputer 150. The external terminal 13 is a terminal for relaying the external request signal ER, i.e., the external interruption request signal. That is, the external terminal 13 is an external interruption input terminal.
The circuit elements of the above-mentioned main circuit are connected to one another through three types of bus lines 51, 52 and 53. The bus line 51 is an address bus line for transmitting an address signal. The bus line 52 is a data bus line for transferring data. The bus line 53 is a control-signal bus line for transferring the control signal between the CPU 5 and the other circuit elements.
Clock MC is supplied to a portion (hereinafter tentatively called a "central circuit") of the main circuit except for the peripheral circuit 9, that is, the CPU 5, ICU 6, memory 7 and the input/output interface 8 through a control circuit 3A and a signal line 31A. The clock MC is a clock signal for use in the central circuit, that is, a main system clock signal. The control circuit 3A is a main-system clock output control circuit for controlling output of the clock MC. The signal line 31A is a signal line for transmitting the clock MC, that is, a main system clock line.
On the other hand, the peripheral circuit 9 is supplied with a clock PC through a control circuit 3B and a signal line 31B. The clock PC is a clock signal for use in the peripheral circuit 9, that is, a peripheral circuit clock signal. The control circuit 3B is a peripheral circuit clock output control circuit, the control circuit 3B being arranged to control the output of the clock PC. The signal line 31B is a signal line for transmitting the clock PC, that is, a peripheral circuit clock line.
Each of the control circuits 3A and 3B is supplied with clock source SC through an oscillation circuit 2 and a signal line 21. Terminals 11 and 12 are connected to the oscillation circuit 2. An external oscillator (a ceramic oscillator or a crystal oscillator) (not shown) is connected to each of the terminals 11 and 12. The connected oscillator performs self-excited oscillation by dint of the operation of an oscillation amplifying device provided for the oscillation circuit 2. As a result, the clock source SC is transmitted from the oscillation circuit 2.
The oscillation circuit 2 is provided with a clock-wave shaping circuit which is arranged in such a manner as to shape the waveform of an original oscillation signal in the form of a sine wave generated as a result of the self-excited oscillation of the oscillator into a rectangular wave. Then, the clock-wave shaping circuit divides the frequency of the rectangular wave, if necessary, and then transmits the signal as the clock source SC. As an alternative to the structure in which the oscillator is connected, an external clock having a shaped waveform may be supplied through the terminal 11. At this time, the terminal 12 is opened or a signal having a phase opposite to that of the external clock which is supplied to the terminal 11 is supplied to the terminal 12.
The operations of the control circuits 3A and 3B are controlled by a control-signal generating circuit 4. That is, the control circuit 3A receives a control signal MCS generated by the control-signal generating circuit 4 and supplied through a signal line 41A, that is, a main-system clock control signal. The control circuit 3A outputs the clock source SC as the clock MC and interrupts the output of the clock MC in response to the control signal MCS. Similarly, the control circuit 3B receives a control signal PCS generated by the control-signal generating circuit 4 and supplied through a signal line 41B, that is, a peripheral circuit clock control signal. The control circuit 3B transmits the clock source SC as the clock PC and interrupts the output of the clock PC in response to the control signal PCS.
Also the oscillation circuit 2 is controlled by the control-signal generating circuit 4. That is, the oscillation circuit 2 receives a control signal ECS generated by the control-signal generating circuit 4 and supplied through a signal line 42, that is, an external clock oscillation control signal. The oscillation circuit 2 transmits the clock source SC and interrupts the output of the clock source SC in response to the control signal ECS.
The oscillation circuit 2, the control circuits 3A and 3B and the control-signal generating circuit 4 constitute a reference-clock control circuit 120 for controlling outputs of clocks MC and PC which are reference clocks (system clocks) for the microcomputer 150.
4. Three types of Clock Mode
The control-signal generating circuit 4 generates the control signals MCS, PCS and ECS in response to various trigger signals transmitted from the CPU 5 and the ICU 6. As a result, the control-signal generating circuit 4 is able to realize three types of clock modes in accordance with the process which is performed by the CPU 5 or in response to the external request signal ER or internal request signal IR supplied to the ICU 6. These plural types of clock modes are employed for the purpose of reducing power consumption of the microcomputer 150 in consideration that electric power is supplied from a battery.
In a usual state of operation in which a special instruction is not issued from the CPU 5 or the ICU 6, the control-signal generating circuit 4 realizes a clock mode in which the clocks MC and PC are transmitted, that is, realizes a normal mode. As a result, the central circuit, such as the CPU 5, memory 7 and the like are supplied with the clock MC and thus operates normally. Also the peripheral circuit 9 is supplied with the clock PC and thus operates normally.
That is, the normal mode corresponds to a usual state of operation in which all circuit elements of the main circuit normally operates. In the normal mode, the microcomputer 150 maximally consumes electric power. If power supply voltage having a sufficiently high level is supplied from a battery or the like to the microcomputer 150, the normal mode is, therefore, selected by the CPU 5 or in response to the request signals ER and IR. As a result, the microcomputer 150 fully functions.
When a trigger signal SQ, i.e., a system clock interruption trigger signal is, in the normal mode, generated by the CPU 5 and supplied to the control-signal generating circuit 4 through a signal line 55, the control-signal generating circuit 4 transmits a control signal MCS to the control circuit 3A and thereby instructs the control circuit 3A to interrupt the output of the clock MC. As a result, a clock mode in which the output of the clock MC is interrupted, whereas the output of the clock PC is continued, i.e., a wait mode is realized. At this time, the level of the signal on the signal line 31A is fixed to a certain signal level (a high level or a low level).
In the wait mode, only the peripheral circuit 9 among the main circuit is supplied with the clock PC. Thus, the peripheral circuit 9 continues the normal operation. The operations of the circuit elements of the central circuit, such as the CPU 5, the memory 7 and the like, which operate in synchronization with the clock MC, are interrupted. As a result, a state is realized in which the signals on the bus lines 51, 52 and 53 are not changed. Thus, the power consumption in the microcomputer 150 is considerably reduced as compared with that in the normal mode.
The wait mode is a clock mode employed on the basis of a technique for reducing power consumption. Therefore, transition from the normal mode to the wait mode is selected when the power supply voltage of the microcomputer 150 has been made to be lower than a predetermined reference level. The selection is performed by the CPU 5.
When the trigger signal EQ, i.e., the external clock oscillation interruption trigger signal is, in the normal mode or the wait mode, generated by the CPU 5 and supplied to the control-signal generating circuit 4 through the signal line 54, the control-signal generating circuit 4 transmits the control signal ECS to interrupt the operation of the oscillation circuit 2. As a result, the output of the clock source SC is interrupted so that transmission of both of the clock MC and PC is interrupted. Alternatively as also well known, the control-signal generating circuit 4 transmits the control signal MCS to instruct the control circuit 3A to interrupt output of the clock MC, and simultaneously, transmits the control signal PCS to instruct the control circuit 3B to interrupt output of the clock PC, so that transmission of both of the clocks MC and PC are interrupted.
As a result, a clock mode in which the transmission of the clock MC and that of the clock PC are interrupted, i.e., a stop mode is realized. At this time, signals on the signal liens 31A and 31B are fixed to certain signal levels (a high level or a low level). In the stop mode, the operations of all circuit elements of the main circuit are interrupted. As a result, the power consumption of the microcomputer 150 is further reduced as compared with that in the wait mode. In particular, when the operation of the oscillation circuit 2 is interrupted, the power consumption is furthermore reduced.
That is, the stop mode is a clock mode employed on the basis of a technique which is capable of furthermore reducing power consumption as compared with that in the wait mode. Therefore, transition from the normal mode or the wait mode to the stop mode is usually selected when the power supply voltage which is supplied to the microcomputer 150 has been made to be lower than another predetermined reference value which is lower than the above-mentioned predetermined reference value. Also this selection is performed by the CPU 5.
On the other hand, transition from the sop mode to the wait mode or the normal mode, i.e., release (termination) of the stop mode is performed when the internal request signal IR or the external request signal ER is supplied to the ICU 6. Similarly, transition from the wait mode to the normal mode, i.e., release (termination) of the wait mode is performed when the internal request signal IR or the external request signal ER is supplied to the ICU 6. When the external request signal ER or the internal request signal IR being supplied, the ICU 6 supplies a trigger signal SS to the control-signal generating circuit 4 and the CPU 5 through a signal line 65. As a result, the release of the stop mode and that of the wait mode are performed.
FIG. 9 is a block diagram showing the internal structure of the ICU 6. The external request signal ER supplied through the external terminal 13 (the number of which is not limited to one) and the internal request signal IR supplied through a signal line 91 are latched by a latch circuit 67. That is, the latch circuit 67 is formed as an interruption-request-signal latch circuit.
The latched external request signal ER and internal request signal IR are judged by a judging circuit 68 whether or not interruption has been permitted. That is, the judging circuit 68 is formed as an interruption permission judging circuit. If the clock mode is in the wait mode or the stop mode, the external request signal ER or the internal request signal IR supplied to release these modes is so judged that the interruption thereof is permitted.
The external request signal ER or the internal request signal IR permitted by the judging circuit 68 to interrupt is supplied to a determination circuit 69. The determination circuit 69 is prepared as an interruption priority order determination circuit which selects a request signal having the highest order from the plurality of the supplied request signals and transmits the selected signal to the signal line 65 as the trigger signal SS.
5. Transition of Clock Mode
Referring back to FIG. 8, the operation of each unit performed at the transition of the clock mode will now be described. Initially, the transition between the normal mode and the wait mode will now be described.
Presupposing that the transition from the wait mode to the normal mode takes place in response to the internal request signal IR, the CPU 5 sets a timer (not shown) included in the peripheral circuit 9 at the transition from the normal mode to the wait mode. Specifically, predetermined data is written in an operation-mode register (not shown) attached to the timer so that a time of occurring of the clock mode transition is set to the timer. Presupposing that the transition from the wait mode to the normal mode occurs in response to the external request signal ER, the timer is not required to be set.
Simultaneously, the CPU 5 performs predetermined setting for the ICU 6. As a result, when the ICU 6 receives the internal request signal IR generated by the timer through the signal line 91, or when the ICU 6 receives the external request signal ER through the external terminal 13, the ICU 6 is brought to a state in which the ICU 6 is able to transmit the trigger signal SS for instructing the release of the wait mode. After the above-mentioned setting operations have been completed, the trigger signal SQ for instructing the clock MC to be fixed is supplied from the CPU 5 to the control-signal generating circuit 4. As a result, the transition from the normal mode to the wait mode is completed in the way described above.
The trigger signal SQ is transmitted when a wait instruction, which is a specific instruction, is executed by the CPU 5 or when writing or reading with respect to a mode entry register (a specific register controlling transition to the wait mode or the stop mode) is performed because the CPU 5 executes the access instruction. As described above, the operation of the CPU 5 is required when the transition from the normal mode to the wait mode is performed.
In the wait mode, the peripheral circuit 9 including the timer continues their operations. Therefore, if the timer has been set, the timer transmits the internal request signal IR when the set time has passed. The internal request signal IR is the internal interruption request signal for requesting the release of the wait mode. The internal request signal IR is supplied to the ICU 6 through the signal line 91.
When the internal request signal IR or the external request signal ER has been supplied to the ICU 6, the ICU 6 supplies the trigger signal SS for instructing restart of supply of the clock MC to the control-signal generating circuit 4 through the signal line 65. Simultaneously, the ICU 6 supplies a predetermined request signal for requesting interruption to the CPU 5 through the foregoing signal line 65.
As a result, supply of the clock MC from the control circuit 3A is started so that the central circuit including the CPU 5 is brought to the operable state. The CPU 5 initially executes the predetermined interruption process in response to the predetermined request signal supplied from the ICU 6. As a result, the CPU 5 restarts the processes in the normal mode, such as data transfer and calculations.
The transition between the normal mode and the stop mode will now be described. Since also the operation of the peripheral circuit 9 is interrupted in the stop mode, the release of the stop mode is not performed in response to the internal request signal IR. The stop mode is released in response to only the external request signal ER. Therefore, the timer of the peripheral circuit 9 is not set when the transition from the normal mode to the stop mode occurs.
On the transition from the normal mode to the stop mode, the CPU 5 performs a predetermined setting for the ICU 6. As a result, the ICU 6 is enabled to transmit the trigger signal SS for instructing the release of the stop mode when the external request signal ER has been supplied to the ICU 6 through the external terminal 13. After the above-mentioned setting has been completed, the trigger signal EQ for instructing fixation of both of the clock MC and clock PC or fixation of the clock source SC is supplied from the CPU 5 to the control-signal generating circuit 4. As a result, the transition from the normal mode to the stop mode is completed in the way described above.
The trigger signal EQ is transmitted when the CPU 5 executes a stop instruction which is one of the specific instructions or when writing in or reading from the mode entry register is performed because the CPU 5 executes an access instruction. As described above, the operation of the CPU 5 is required when the transition from the normal mode to the stop mode is performed.
When the ICU 6 is supplied with the external request signal ER during the stop mode, the ICU 6 supplies the trigger signal SS for instructing supply of the clock MC and the clock PC or restart of the supply of the clock source SC to the control-signal generating circuit 4 through the signal line 65. Simultaneously, the ICU 6 supplies a predetermined request signal for requesting execution of the interruption to the CPU 5 through the same signal line 65.
As a result, supply of the clocks MC and PC is started so that the central circuit, which includes the CPU 5, and the peripheral circuit 9 are brought to operable state. The CPU 5 initially executes a predetermined interruption process in response to a predetermined request signal supplied from the ICU 6. As a result, the CPU 5 restarts the processes of the normal mode, such as the data transfer and calculations.
On the transition from the wait mode to the stop mode, each unit operates similarly to that on the transition from the normal mode to the stop mode operates. That is, the CPU 5, the operation of which has been suspended during the wait mode temporarily, restarts the operation to perform the transition of the clock mode from the wait mode to the stop mode, and thereby performs a predetermined operation for the ICU 6 and the control-signal generating circuit 4. For this purpose, also the supply of the clock MC is, although temporarily, restarted. That is, the transition from the wait mode to the stop mode is performed in such a manner that the clock mode is temporarily returned to the normal mode.
Also the transition from the stop mode to the wait mode is performed similarly to the transition from the stop mode to the normal mode. That is, the transition from the stop mode to the wait mode is started in response to the external request signal ER supplied to the ICU 6 through the external terminal 13. More specifically, when the ICU 6 is supplied with the external request signal ER during the stop mode, the ICU 6 supplies the trigger signal SS for instructing restart of supply of the clock PC or the clock source SC to the control-signal generating circuit 4 through the signal line 65.
As a result, the supply of the clock PC is started so that the peripheral circuit 9 is brought to the operable state. Differently from the transition to the normal mode, the trigger signal SS is not supplied to the CPU 5. Thus, the transition to the wait mode is completed without the CPU 5 performing the interruption process.
As described above, the microcomputer 150 is so structured that the transition of the operating state is performed among three clock modes in response to the level of the power supply voltage. Therefore, power consumption can significantly be reduced. As a result, the above-mentioned microcomputer has widely been used in a small-size portable device having a battery as a power source.
However, the microcomputer 150 which is a conventional device suffers from excessively large power consumption when transition of the clock mode to a small power consumption mode (a clock mode, such as the wait mode or stop mode, which is a clock mode different from the normal mode, for reducing power consumption) is performed as will be described below.
As described above, all of the transition from the normal mode to the wait mode, from the normal mode to the stop mode and from the wait mode to the stop mode are performed when the CPU 5 executes a specific instruction, such as the wait instruction or the stop instruction or when writing in or reading from the mode entry register is performed because the CPU 5 executes the access instruction. That is, the transition to the small power consumption mode requires the operation of the CPU 5 and the reading operation of the memory 7 to be read by the CPU 5.
In order to perform the above-mentioned operation, the microcomputer 150, despite temporarily, consumes electric power in a quantity considerably large as compared with the power consumption in the wait mode or the stop mode. The peak power consumption which takes place on the transition to the small power consumption mode sometimes raises a critical problem for a small size portable device which require a battery as the power source.
If a device having the microcomputer 150 mounted thereof is operated by a battery, there is apprehension that the remaining quantity of electric power in the battery is reduced and the power supply voltage supplied from the battery is reduced to a level (the operating limit voltage) corresponding to the operating limit for the CPU 5. Also in this case, the transition of the clock mode from the wait mode to the stop mode for the purpose of reducing power consumption requires the above-mentioned operation which consumes large electric power despite temporarily.
Also in a case where the transition of the clock mode from the normal mode to the wait mode is required during the normal mode because of the reduction in the power supply voltage from the battery, the transition to the wait mode inevitably encounters the peak power consumption. Thus, when the remaining electric power in the battery has been reduced and thus power consumption must be reduced, consumption of large electric power, which runs counter the power saving, must be performed despite temporarily.
Therefore, when the transition to the small power consumption mode is performed because of small remaining electric power, electric power is consumed at a peak level. Accordingly, the power supply voltage from the battery has sometimes been reduced to the operating limit level for the CPU 5. As a result, the CPU 5 cannot sometimes normally be operated, thus sometimes causing runaway thereof. If runaway of the CPU 5 takes place, data stored in a volatile memory, such as a RAM, included in the memory 7 cannot always normally be stored because of the unexpected operation of the CPU 5. Therefore, the CPU 5 cannot sometimes be restored to the previous state even after the voltage of the battery has been restored to the normal level.